1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device suitable for noise reduction.
2. Description of Related Art
In recent years, low voltage and high speed techniques have been advanced in systems equipped with an ASIC (Application Specific Integrated Circuit) product. Also, in the field of SRAMs of a semiconductor memory device provided in the ASIC product, the low voltage and high speed techniques have been required. Therefore, miniaturization of semiconductor processes is advancing.
Along with the miniaturization of semiconductor processes, capacitances of bit lines which select memory cells for storing data and capacitances of signal lines (for examples read lines) which connect between a selected bit line and a sense amplifier for reading out data become smaller. Therefore, the ratio between the total capacitance of the bit lines and read lines, and the coupling capacitance of these lines under the effect of the other lines becomes larger. Thus, a countermeasure to reduce the effect of the coupling capacitance on the performance of the SRAM circuit has been required (for example, see Japanese Unexamined Patent Application Publication No. 10-326873).
FIG. 8 is a block diagram showing a semiconductor memory device according to the related art. The circuit shown in FIG. 8 includes m×n (m and n are natural numbers) number of memory cells MC00 to MC(m−1)(n−1), n number of precharge circuits PC0 to PC(n−1), n number of column selectors CSR0 to CSR(n−1), a precharge circuit PCs, and a sense amplifier SA.
The memory cells MC00 to MC(m−1)(n−1) are arranged at nodes between word lines WLs and bit line pairs DT/DBs. The memory cells MC00 to MC(m−1)(n−1) are arranged in a matrix. Note that the word lines WLs include word lines WL0 to WL(m−1). The bit line pairs DT/DBs include bit line pairs DT0/DB0 to DT(n−1)/DB(n−1).
Memory cell groups arranged in n columns are connected to a common read line pair YDT/YDB through the corresponding precharge circuits PC0 to PC(n−1) and the corresponding column selectors CSR0 to CSR(n−1). The sense amplifier SA amplifies a potential difference of the read line pair YDT/YDB and outputs the amplified potential difference as readout data from one of the memory cells.
For example, a case is explained in which the memory cell MC00 is selected. First, all the bit line pairs are precharged. Next, the word line WL0 is selected (FIG. 9A). Then, the potentials of all the bit line pairs change according to charges stored in the memory cells connected to the word line WL0 (FIGS. 9B and 9C). Further, the bit line pair DT0/DB0 is selected by the column selector CSR0.
When the bit line pair DT0/DB0 is selected, the potential of the bit line DT0 is transmitted to the read line YDT (YDT shown in FIG. 9D) and is input to one input terminal of the sense amplifier SA. Further, the potential of the bit line DB0 is transmitted to the read line YDB (YDB shown in FIG. 9D) and is input to the other input terminal of the sense amplifier SA. The sense amplifier SA amplifies the potential difference of the read line pair YDT/YDB, thereby reading out data from the memory cell MC00.
In the circuit shown in FIG. 8, different parasitic capacitances are added to the read lines YDT and YDB in accordance with the potential variations of the bit line pairs in non-selected columns (for example, the bit line pair DT(n−1)/DB(n−1)). Specifically, the read line YDT is connected to the bit lines DT0 to DT(n−1). When the bit line DT0 is selected (DT0 shown in FIG. 10B), the potential of the read line YDT mainly reflects the potential of the bit line DT0. However, the parasitic capacitances of the bit lines DT1 to DT(n−1) are also added to the read line YDT (YDT shown in FIG. 10D) because the read line YDT is connected to the bit lines DT1 to DT(n−1) which are not selected (see FIG. 10C). Similarly, the read line YDB is connected to the bit lines DB0 to DB(n−1). When the bit line DB0 is selected (DB0 shown in FIG. 10B), the potential of the read line YDB mainly reflects the potential of the bit line DB0. However, the parasitic capacitances of the bit lines DB1 to DB(n−1) are also added to the read line YDB (YDB shown in FIG. 10D) because the read line YDB is connected to the bit lines DB1 to DB(n−1) which are not selected (see FIG. 10C).
The potential differences between the bit lines DT and DB vary depending on data (0 or 1) stored in each corresponding memory cell. Therefore, the effects of the parasitic capacitances added from the non-selected bit lines to the read line pair YDT/YDB are different from each other. At worst, it becomes impossible to read out data accurately because the potential difference of the bit line pair DT/DB depending on the data stored in the memory cell MC00 decreases under the effect of these parasitic capacitances (see FIG. 10D). Otherwise, it is necessary to set a considerably large margin for reading out the data. Therefore, the circuit shown in FIG. 8 has a problem that it is impossible to read out data accurately.
A solution to this problem is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 10-326873. FIG. 11 illustrates a semiconductor integrated circuit disclosed in Japanese Unexamined Patent Application Publication No. 10-326873. The circuit shown in FIG. 11 includes a common bit line BL connected to each of bit lines (BL1, BL2), and a reference bit line KBL charged with a reference potential to determine the potential of the bit line BL. The bit line BL and the reference bit line KBL are provided with dummy elements to set the parasitic capacitance of the bit line BL to be substantially equal to the parasitic capacitance of the reference bit line KBL. This makes it possible to improve the noise-resistant performance.
However, switch elements may generate an unintended parasitic capacitance. Specifically, the circuit shown in FIG. 11 also includes a number of switch elements which connect each bit line (BL1, BL2) to the common bit line BL. The switch elements in non-selected columns include parasitic capacitances. Moreover, the parasitic capacitance of each switch element is influenced by the potential of the corresponding bit line, so that the value of the parasitic capacitance is unstable. Therefore, there arises a problem that cannot be solved by the method used in the circuit shown in FIG. 11 which adds the parasitic capacitance of the dummy elements to the reference of reading out data.
A description is given of a problem that may occur in the circuit shown in FIG. 11, when the data read out to the bit line BL1 is “H”, the data read out to the bit line BL2 is “L”, and the data of the bit line BL1 is read out.
In this case, a gate potential of a transistor T15 indicates the potential of the bit line BL1 (see FIG. 12B). However, the gate potential of the transistor T15 (see FIG. 12D) changes in accordance with the potential variation of the bit line BL2 (see FIG. 12C) under the effect of the parasitic capacitances existing between the source and the drain of the transistors T9 and T10. In other words, noise occurs in the gate potential of the transistor T15 in accordance with the potential of the bit line BL2 which is not selected. Specifically, the data read out to the bit line BL2 is “L”, so that the gate potential of the transistor T15 decreases compared to the case where the noise has a small effect (see FIG. 12D). Note that the gate terminal of the transistor T15 and the drain terminal (which outputs an output signal DO) of the transistor T16 are connected to each other through a capacitor C1. Therefore, a potential applied to one terminal of the capacitor C1 decreases in accordance with a decrease in the gate potential of the transistor T15. Then, the potential of the output signal DO decreases. That is, the circuit shown in FIG. 11 has a problem that it is impossible to read out data accurately.